RESTUCCIA, FRANCESCO
 Distribuzione geografica
Continente #
NA - Nord America 261
EU - Europa 244
AS - Asia 72
Totale 577
Nazione #
US - Stati Uniti d'America 260
IT - Italia 99
CN - Cina 30
GB - Regno Unito 30
IE - Irlanda 25
SG - Singapore 25
DE - Germania 20
FR - Francia 14
RU - Federazione Russa 14
UA - Ucraina 11
ES - Italia 9
VN - Vietnam 8
SE - Svezia 7
FI - Finlandia 6
IN - India 4
AT - Austria 2
BE - Belgio 2
PK - Pakistan 2
PT - Portogallo 2
CA - Canada 1
CZ - Repubblica Ceca 1
IR - Iran 1
KR - Corea 1
LK - Sri Lanka 1
LT - Lituania 1
NL - Olanda 1
Totale 577
Città #
Chandler 52
Dublin 24
Singapore 18
Fairfield 15
Varenna 15
Ashburn 12
Pisa 12
San Mateo 12
Seattle 11
Stevenage 11
Falls Church 10
Beijing 9
Boardman 9
Jacksonville 9
Wilmington 9
Cambridge 8
Santa Clara 8
Southend 8
Brooklyn 7
Dongguan 7
Houston 7
Rome 7
Turin 7
Woodbridge 7
Fremont 6
Helsinki 6
Lawrence 6
Milan 6
Portsmouth 6
Barcelona 5
Buti 5
Dong Ket 5
Munich 5
Modena 4
San Diego 4
Assago 3
Hanover 3
L'Hospitalet de Llobregat 3
London 3
Mumbai 3
Ann Arbor 2
Bisignano 2
Bolzano 2
Brussels 2
Busto Garolfo 2
Como 2
Giulianova 2
Hamburg 2
Hebei 2
Isorella 2
Livorno 2
Nanjing 2
Scarperia e San Piero 2
Shenyang 2
Vienna 2
Washington 2
Ajjavara 1
Amsterdam 1
Ascheberg 1
Badia Polesine 1
Barbariga 1
Beaverton 1
Boulogne-Billancourt 1
Brno 1
Colombo 1
Empoli 1
Figino 1
Follonica 1
Harbin 1
Incheon 1
Inglewood 1
Las Vegas 1
Limerick 1
Madrid 1
Miami 1
Padova 1
Palermo 1
Palo Alto 1
Polverigi 1
Porto 1
Redmond 1
San Giorgio delle Pertiche 1
San Jose 1
Sandston 1
Shanghai 1
Shenzhen 1
Terzigno 1
Toronto 1
Totale 431
Nome #
Is your bus arbiter really fair? Restoring fairness in axi interconnects for FPGA SOCs 150
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC 100
AXI HyperConnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC 79
ARTe: Providing real-time multitasking to Arduino 70
Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms 66
Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs 63
PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms 61
Totale 589
Categoria #
all - tutte 4.934
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 4.934


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/202019 0 0 0 0 0 4 3 3 2 2 0 5
2020/2021101 9 7 4 6 10 6 12 5 7 9 7 19
2021/2022130 5 10 7 8 3 11 13 19 2 23 12 17
2022/2023101 6 12 11 20 13 9 2 4 15 1 2 6
2023/2024126 19 1 12 14 7 26 7 4 7 8 6 15
2024/2025112 25 8 28 4 26 21 0 0 0 0 0 0
Totale 589